Talent 101 Circuit

Norma – Physical Design Engineer  

• Performed RTL Synthesis, Physical implementation through floor planning, auto place and route, clock tree synthesis and static timing analysis at 22nm
• Developed automated scripts using TCL, Perl with EDA tools to fix different violations like maxcap, maxtran, hold, setup and DRC
• Improved test coverage results by 25% by developing testability flow for three EDA tools and managed eight design automation tools

• Worked closely with tool vendors for technology specific feature enhancements for advanced Intel node process
• Documented tool usage procedures, prepared training documents and presented information to customers
• Managed and executed assigned design section of a micro server chip project using Synopsys tools
• Providing direction and recommendations to respective department team members on timing, power and area of semiconductor chip
• Designed and developed reference flows for Intel Custom Foundry clients, debugged client issues and advised clients on multiple projects and worked with QA team to ensure good quality of results