Talent 101 Circuit

Javier – IC Layout Designer

• Principal level RF/Analog/Mixed-Signal IC Layout Designer  with extensive experience in layout floor planning, standard cell planning, hierarchical layout assembly, device matching, place-and-route (P&R) of large digital and analog blocks, shielding and guard ringing, DFM, tape out GDSII format and E-beam mask generation
• Broad and deep knowledge in multiple complex designs for PMIC, analog, digital, mixed-signal, high speed GHz RF, Datapath and standard cells

Samuel – Senior IC Layout Engineer  

• Solid history of establishing and maintaining positive working relationships with Design, Product and Test Engineers
• Analytical and resourceful in solving new and challenging problems 
• Self-motivated individual contributor and positive team player  
• Goal-directed with focus on details and follow-through
• Cadence Virtuoso and VXL

Ti – Analog IC Design Engineer

• Designed analog-integrated circuits for automotive applications, including band-gap circuitry, oscillator, voltage monitor, power supply unit, driver and fall-monitoring circuitry.

• Interacted with customers to address needs and define design specifications.

• Determined design approaches, circuit topology and verified through simulation.

• Reviewed IC layout and evaluation-board design.

Marina – IC Layout Design Engineer

• Proficiency in LVS, DRC, DFM, ERC with Hercules VUE (Synopsys), Caliber (MentorG).

• Experience in CADENCE layout tools, Virtuoso & Virtuoso Layout-XL.

• Working knowledge and self-sufficient in UNIX terminal operations.

• In-depth knowledge in full custom layout design in 16nm(12LM), exposure to 7nm(14M).