Kane – Physical Design Engineer
- Physical Design
- Block level Implementation and physical design of various blocks for 7nm processor.
- Synthesis, place and route, timing, clock tree synthesis, scan chain. IR and EM study and fixes. DRC, LVS clean up
- Execution Unit
- Fetch Unit
- Memory Subsystem
- Write back Unit
- Load Store Unit
- Switching and Arrival Queue
- ASIC
- Power analysis for ZSP400 and ZSP500 subsystem
- LCD driver design in FPGA for ZSP500 subsystem
- Synthesis works
- Low Power Methodology development
MSEE - Georgia Tech, Atlanta GA