Talent 101 Circuit

Senior VLSI Design Engineer Available NOW

Posted on February 05, 2018 by Kent Smith

Ramesh - Senior VLSI Design Engineer

  • Five years of experience as Physical Layer IP Team lead, contributed mainly as Lead Designer.
  • Contributed to multiple activities from Pre-sales to Silicon bring up of PHY IPs.
  • Eleven years of Career in semiconductor field covering Design, Synthesis, STA, FPGA, DFT.
  • Excellent in defining timing constraints including tight Analog to Digital interface signals.
  • Performed STA for 6 Projects.
  • Good combination of strong design skills with in depth timing visualization.
  • Verilog RTL designer with experience in Multi Clock Domain Designs.
  • Expertise in SOC level and IP level DFT Design, Verification and Silicon testing including DC and at speed scan, Memory BIST.
  • Closely works with STA / PnR team to address challenging timing / area closures, ECOs.
  • Performed design evaluation in Xilinx FPGAs.
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AMS Engineer with 10+ years of experience Available

Posted on February 02, 2018 by Kent Smith

Vinod – AMS Engineer

  • 10+ years of experience in Analog, Mixed Signal and High-speed IO Layout Design of modules and Chip level tasks.
  • Worked on various technology nodes like 180nm, to 10nm
  • Proficient in layout design using Cadence Virtuoso XL and Genesys
  • Custom layout design of blocks, IPs and Full Chip Integration
  • Floor planning, Power planning and Area estimation of modules
  • Special planning during placement considering density, HV,EMIR,DRC in deep submicron nodes
  • Physical Verification of the layout designs
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Senior Verification Engineer with 8+ Years Experience Available

Posted on January 31, 2018 by Kent Smith

Sham - Senior Verification Engineer

  • 8yrs+ overall industry experience in Mixed Signal and Digital Verification
  • Experience in System Verilog and UVM, PSL, and SVA Assertions
  • Behavioral Modeling of Analog Modules in SV, VAMS, and VHDL
  • Model Vs. Spice Simulations, Analog Mixed Signal Co-Simulations
  • Verification of Sound wire, I2C, AHB, and DMA protocols
  • Functional and Code coverage Analysis
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Physical Design & Digital Back-end Engineer Available

Posted on January 29, 2018 by Kent Smith

Jay – Physical Design/Digital Back end Engineer (Available Immediately)

 

  • Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule.
  • Working on complex digital on top lower power design.
  • Define and verify power intent.
  • RTL synthesis.
  • Equivalence check.
  • Floorplan.
  • Define power domain and power routing.
  • Insert power switches.
  • Isolation and retention cells placement.
  • CTS and routing.
  • STA timing analysis.
  • Worked on top level timing closure.
  • Bump placement, place bumps with various patterns, assign signals to bumps.
  • Floorplan, pin placement, RAM placement, power meshes, analog block placement.
  • Clock tree generation using ccopt.
  • Worked on timing analysis/closure at both top and block level.
  • Worked on diversified designs of high utilizations, irregular shapes, and complex clock tree structure with Encounter Foundation Flow.
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FPGA Developer & Scripting Expert Available Immediately

Posted on January 26, 2018 by Kent Smith

Ariel – FPGA Developer/Scripting Expert (Available Immediately)

  • Writes/debugs Python-based firmware test programs for a new device, including battery.
  • Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
  • Responsible for the ROM contents on Veridian. Additionally responsible for the new Flash programming and erase routines for the customer. Develops random test bench to exercise the Flash memory.
  • Wrote a python emulator of the Veridian device. The ARM cortex M0+ core was modelled along with RAM, ROM, FLASH, UART and other blocks. The emulator reads the ELF file containing the binary code compiled by the Keil tools and provides a near clock accurate execution model of that code running on Veridian. This enables the Veridian ROM image to be debugged in advance of Silicon.
  • Developed a flash emulation on a FPGA. Through a ROM based C program, emulates the Flash API library to allow the Veridian customer to develop their firmware on a FPGA with confidence that it will function on the silicon when it is finished.
  • Developed a Verilog AMS generator to interface the digital and analog portions of Veridian together. This enabled the design team to simulate concurrently the digital and analog design databases.
  • Developed a Verilog generator that instantiates the level shifters between the different power domains on Veridian. The Python programs reads an Excel spreadsheet to get a template and then generates a Verilog netlists as per that template.
  • MSEE, Purdue University, GPA: 5.9/6.0
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Design Engineer Experienced in Analog, Mixed Signal & High-Performance RF IC Design

Posted on January 24, 2018 by Kent Smith

Jared – Analog/Mixed Signal Design Engineer

  • Analog, mixed signal, and high-performance RF IC design.
  • Switching power converters, LDOs, DC/DC, Buck and Boost, and Power ICs.
  • Hall sensors for automotive industries.
  • Analog interface circuits for MRAM, DDR interface.
  • Ultra-high accuracy CMOS frequency references with mitigated aging.
  • High-performance RF IC Design and Analog/Mixed Signal IC Design.
  • State-of-art low-noise and low distortion RF/analog front-ends.
  • Wireless transceiver system design, video-receivers and mass-storage channels.
  • IC subsystem design: PLL’s, DDL’s, gain-controls and gm-C filters.
  • CMOS, BiCMOS and bipolar IC block design such as: LNAs, mixers, phase shifters, amplifiers, comparators, PAs, VCOs, charge pumps, ADCs, DACs, LDOs, power supplies, and bias blocks.
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Analog/Mixed Signal Design Engineer Available

Posted on January 22, 2018 by Kent Smith

Kevin– Analog/Mixed Signal Design Engineer

  • Buck, Boost, LDO, Regulators ADC
    • 1.2V buck converter, 50mA output
    • 3.3V boost converter, 150mA output
  • Current-limited voltage source for PoDL detect circuit.
  • Sense chopper amplifier for PoE.
  • Audio codec Development
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Manufacturing Mechanical Engineer Available

Posted on January 19, 2018 by Kent Smith

 Ayobe – Manufacturing Mechanical Engineer

  • Mechanical Engineering
  • Process Development
  • Operational Reliability
  • Process Control/Reengineering
  • Component Testing
  • Regulatory Compliance
  • Project Management
  • Contract Administration
  • Operations/Maintenance
  • Designing and implementing cost effective solutions within complex R&D
  • Pilot scale and manufacturing environments for commercial and governmental organizations
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Hardware/Firmware Engineer with Experience Developing Verilog Generators & Flash Emulation

Posted on December 18, 2017 by Kent Smith

RICO – HARDWARE/FIRMWARE ENGINEER (AVAILABLE IMMEDIATELY) 


  • Writes/debugs Python based firmware test programs for a new device, including battery.
  • Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
  • Responsible for the ROM contents on Veridian. Additionally responsible for the new Flash programming and erase routines for the customer. Develops random test bench to exercise the Flash memory.
  • Wrote a python emulator of the Veridian device. The ARM cortex M0+ core was modelled along with RAM, ROM, FLASH, UART and other blocks. The emulator reads the ELF file containing the binary code compiled by the Keil tools and provides a near clock accurate execution model of that code running on Veridian. This enables the Veridian ROM image to be debugged in advance of Silicon.
  • Developed a flash emulation on a FPGA. Through a ROM based C program, emulates the Flash API library to allow the Veridian customer to develop their firmware on a FPGA with confidence that it will function on the silicon when it is finished.
  • Developed a Verilog AMS generator to interface the digital and analog portions of Veridian together. This enabled the design team to simulate concurrently the digital and analog design databases.
  • Developed a Verilog generator that instantiates the level shifters between the different power domains on Veridian. The Python programs reads an Excel spreadsheet to get a template and then generates a Verilog netlists as per that template.
  • MSEE, Purdue University
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Test Technician Specialized in High-Throughput Testing of WCSP

Posted on December 15, 2017 by Kent Smith

Honorio – Test/Qual Technician

  • Conducted hand-screening of prototype IC units on ATE and bench EVM platforms to support customer sample demand.
  • Specialized in high-throughput testing of smaller package sizes, including WCSP packages on the order of 1.5 mm dimension.
  • Such hand activity routinely involved quantities in the thousands at rates ranging from 100 units per hour to 500 units per hour, and demanded innovation of customized testing approaches and apparatus.
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