Talent CIRCUIT

Design Verification Engineer with Experience in block and SOC (Available Now)

Posted on April 06, 2018 by Kent Smith

Extensive experience in the Design Verification in both block and SoC levels
Skilled in directed and constrained-random test benches
Proficient in Object-Oriented programming
Languages – System Verilog, Verilog, SVA, C, Perl, Shell Scripts, assembly (e200, e500, HC08, HC12)
Verification methodologies – UVM, VMM
Simulators – VCS, NC Verilog (incisive), Verilog XL

Posted on April 04, 2018 by Kent Smith

Posted on February 05, 2018 by Kent Smith

Five years of experience as Physical Layer IP Team lead, contributed mainly as Lead Designer.
Contributed to multiple activities from Pre-sales to Silicon bring up of PHY IPs.
Eleven years of Career in semiconductor field covering Design, Synthesis, STA, FPGA, DFT.
Excellent in defining timing constraints including tight Analog to Digital interface signals.
Performed STA for 6 Projects.
Good combination of strong design skills with in depth timing visualization.
Verilog RTL designer with experience in Multi Clock Domain Designs.
Expertise in SOC level and IP level DFT Design, Verification and Silicon testing including DC and at speed scan, Memory BIST.
Closely works with STA / PnR team to address challenging timing / area closures, ECOs.
Performed design evaluation in Xilinx FPGAs.

Posted on August 12, 2016 by Kent Smith

Product management and marketing of ARM and Power Architecture SoCs for networking and high-performance embedded applications.
Managed all aspects of product lifecycle for several QorIQ family embedded processors resulting in $1B+ design wins and $2B+ new funnel opportunities.
Networked Embedded Computers, x86 Compute, Network Appliance and Storage Servers.
Bachelor of Science in Engineering - Electrical Engineering/Computer Science.

Posted on August 10, 2016 by Kent Smith

Excellent in VLSI design flow which includes RTL designing using Verilog, verification of it using System Verilog and physical implementation using IC and DC Complier.
Hands on experience with full custom IC design while designing a 64x32 SRAM Memory using Custom designer and verifying it through DRC and LVS checks.
C programming and a working knowledge of PERL.
Masters of Science in Embedded Electrical and Computer Systems.