Talent 101 Circuit

Digital VLSI Engineer with Experience in RTL Design and Logic Synthesis

Posted on June 25, 2018 by Nick Trompert

Rohan - Digital VLSI Engineer (Mid-level)

  • Experience in RTL Design (with Verilog HDL and System Verilog) and Logic Synthesis.
  • Hands-on experience of Constraint Random based, System Verilog Assertion based and Coverage driven Functional Verification.
  • In-depth knowledge on CMOS Integrated Circuits, Digital Logic Design, ASIC & FPGA Design flow, Static Timing Analysis (STA), Power Analysis & Optimization and DFT (Scan).
  • Good understanding of Physical design flow (Floor planning, Clock Tree Synthesis, place and Route) and Physical Verification.
  • Good theoretical knowledge on Computer Architecture and organization (Pipelining, Cache Memory and Tomasulo Algorithm).
  • Proficient in Perl scripting using Perl Regular Expressions and Hashes.
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