Talent 101 Circuit

Jaycee – Physical Design Engineer 

• Core experience centered around physical design of large complex CMOS ASIC SOC designs using industry standard tools i.e. innovus, ICC, talus and PrimeTime. 
• Experienced in synthesis, formal verification, floor planning (block and top level), power creation and repair, timing driven placement and routing, CTS, timing convergence and analysis, noise convergence and analysis, LVS and DRC.

Lorenz – Physical Design Engineer  

• Physical Design
• Block level Implementation and physical design of various blocks for 7nm processor. 
• Synthesis, place and route, timing, clock tree synthesis, scan chain.  IR and EM study and fixes. DRC, LVS clean up
• Execution Unit

Kale – Custom IC Layout Engineer   

• IC physical design engineer with over 10 years of experience which includes full custom analog, digital place and route, and chip-level mixed-signal integration. 
• Comfortable at all levels of hierarchy and leading teams. 
• Experienced in defining, documenting, and training team members in Layout Methodologies for the most current process nodes.

Sangh – Physical Design/Digital Back End Engineer 

• Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule
• Working on complex digital on top lower power design
• Define and verify power intent 
• RTL synthesis

Dianne – Digital Design Engineer

• A senior engineer with extensive experience in the semiconductor industry.
• Experienced in cache memory design and test, chip clocking and clock methodology, software development, front end verification, ARM Microprocessor architecture, CPU Micro Architecture, product development, post Si validation, and testing digital circuit devices.
• Results oriented individual contributor and a motivated team player who is committed to learning and generating new technologies and methodologies.

Norma – Physical Design Engineer  

• Performed RTL Synthesis, Physical implementation through floor planning, auto place and route, clock tree synthesis and static timing analysis at 22nm
• Developed automated scripts using TCL, Perl with EDA tools to fix different violations like maxcap, maxtran, hold, setup and DRC
• Improved test coverage results by 25% by developing testability flow for three EDA tools and managed eight design automation tools

Shiva – Physical Design Engineer 

• Physical Design Engineer in the field of Semiconductor design.
• Experienced in ASIC design flow from RTL to GDSII: RTL Synthesis, Floor Planning, Power Planning, Placement and trail routing, CTS, Routing, Parasitic Extraction, STA & SI, and DRC/LVS.
• Hands on experience in RTL design and verification of digital design using Verilog.
• Proficient scripting skills in Perl, TCL, and Shell.
• M.S. in Electrical Engineering

Barbara – Senior ASIC Physical Design Engineer 

• 20+ years as a physical designer and 10 tape-outs, from netlist to GDS
• 10+ years of methodology development, understanding and using other company’s methodology
• VLSI design work & custom layout using backend tools from Synopsys(ICC1), Cadence(Innovus)
• Large 28 million gate design, physical partition into three blocks. Intel 10nm process and library and IP
• Create and developed a power estimate to create IR/EM correct power rails using Synopsys tools for TSMC flow
• Extensive use of portable scripting languages for tools flow development
• Versed in Microsoft EXCEL spreadsheet for calculations

Charbel – Physical Design Engineer 

• Core experience centered on physical design of large complex CMOS, ASIC, SOC Designs using industry standard tools i.e. Innovus, ICC, talus, and Primetime.
• Responsible for synthesis, formal verification, floor planning (block and top level), power creation and repair, timing driven placement and routing, CTS, timing convergence and analysis, noise convergence and analysis, LVS and DRC.
• Proficient in Cadence's SOC FE, Synopsys' ICC and talus performing synthesis, place and route, timing closure and power analysis.
• Intermediate user of Mentor’s Olympus tool. 
• Proficient user of PTSI from Synopsys and Calibre performing LVS/DRC. 

Lui – Physical Design Engineer

• Physical design engineer with experience in mixed-signal circuit design.
• Experienced in all phases of circuit / physical design including synthesis, static timing analysis, optimization, and implementation.  
• Experienced in technical project management, high-speed memory design (SRAM), and design flow development.
• Physical Design, Mixed-Signal Design, Project Management, SOC Encounter and RTL to GDS
• Static Timing Analysis, Circuit Simulation, Synthesis, Spectre/MDL and EMIR
• Magma, Virtuoso, ICC, HSPICE and Cadence
• TCL, Synopsys, Primetime, RTL Compiler and ASIC
• B.S. in Electrical Engineering