Jaycee – Physical Design Engineer
- Core experience centered around physical design of large complex CMOS ASIC SOC designs using industry standard tools i.e. innovus, ICC, talus and PrimeTime.
- Experienced in synthesis, formal verification, floor planning (block and top level), power creation and repair, timing driven placement and routing, CTS, timing convergence and analysis, noise convergence and analysis, LVS and DRC.
- Goal-oriented and have taped out successfully many designs individually or as a significant contributor.
- Proficient in Cadence's SOC FE , Synopsys' ICC and talus performing synthesis, place and route, timing closure and power analysis.
- Intermediate user of Mentor’s Olmpus tool.
- Proficient user of PTSI from Synopsys and Calibre performing LVS/DRC.
- Intermediate skill in tcl development.
- MS in Electrical Engineering.