Talent CIRCUIT

Digital VLSI Engineer with Experience in RTL Design and Logic Synthesis

Posted on June 25, 2018 by Nick Trompert

Experience in RTL Design (with Verilog HDL and System Verilog) and Logic Synthesis.
Hands-on experience of Constraint Random based, System Verilog Assertion based and Coverage driven Functional Verification.
In-depth knowledge on CMOS Integrated Circuits, Digital Logic Design, ASIC & FPGA Design flow, Static Timing Analysis (STA), Power Analysis & Optimization and DFT (Scan).
Good understanding of Physical design flow (Floor planning, Clock Tree Synthesis, place and Route) and Physical Verification.
Good theoretical knowledge on Computer Architecture and organization (Pipelining, Cache Memory and Tomasulo Algorithm).
Proficient in Perl scripting using Perl Regular Expressions and Hashes.

Posted on March 23, 2018 by Kent Smith

7yrs overall industry experience – IP verification (RTL and GLS), FPGA verification and RTL Design.
Experience in Digital Verification (testbench environment, models, checkers, drivers, functional coverage, assertions and test case development in system Verilog and Verilog languages).
Experience in using scripting languages like Perl for pre/post-processing of results.
Experience in Verilog, SV and UVM test bench environments.
Experience in RTL design.
Experience in different serial and parallel bus protocols.

Posted on February 05, 2018 by Kent Smith

Five years of experience as Physical Layer IP Team lead, contributed mainly as Lead Designer.
Contributed to multiple activities from Pre-sales to Silicon bring up of PHY IPs.
Eleven years of Career in semiconductor field covering Design, Synthesis, STA, FPGA, DFT.
Excellent in defining timing constraints including tight Analog to Digital interface signals.
Performed STA for 6 Projects.
Good combination of strong design skills with in depth timing visualization.
Verilog RTL designer with experience in Multi Clock Domain Designs.
Expertise in SOC level and IP level DFT Design, Verification and Silicon testing including DC and at speed scan, Memory BIST.
Closely works with STA / PnR team to address challenging timing / area closures, ECOs.
Performed design evaluation in Xilinx FPGAs.

Posted on October 26, 2016 by Kent Smith

Experience in RTL Design (with Verilog HDL and System Verilog) and Logic Synthesis.
Hands-on experience of Constraint Random based, System Verilog Assertion based, and Coverage driven Functional Verification.
In-depth knowledge on CMOS Integrated Circuits, Digital Logic Design, ASIC & FPGA Design flow, Static Timing Analysis (STA), Power Analysis & Optimization and DFT (Scan).