Talent 101 Circuit

Digital VLSI Engineer with Experience in RTL Design and Logic Synthesis

Posted on June 25, 2018 by Nick Trompert

Rohan - Digital VLSI Engineer (Mid-level)

  • Experience in RTL Design (with Verilog HDL and System Verilog) and Logic Synthesis.
  • Hands-on experience of Constraint Random based, System Verilog Assertion based and Coverage driven Functional Verification.
  • In-depth knowledge on CMOS Integrated Circuits, Digital Logic Design, ASIC & FPGA Design flow, Static Timing Analysis (STA), Power Analysis & Optimization and DFT (Scan).
  • Good understanding of Physical design flow (Floor planning, Clock Tree Synthesis, place and Route) and Physical Verification.
  • Good theoretical knowledge on Computer Architecture and organization (Pipelining, Cache Memory and Tomasulo Algorithm).
  • Proficient in Perl scripting using Perl Regular Expressions and Hashes.
  • Protocols: UART, I2C, SPI, AMBA – APB, AHB and AXI.
  • EDA/ Software Tools: Synopsys VCS, Synopsys DC, Cadence NC Sim, Cadence Virtuoso, Altera Quartus II, ModelSim-Altera, Xilinx ISE, Xilinx Vivado, SPICE, MATLAB.
  • Languages: Verilog HDL, System Verilog HDVL, C/ C++ (Object Oriented) Programming, PERL Scripting, UNIX Shell Scripting.

Contact Us About This Candidate

Topics: VLSI, engineer, digital VLSI engineer

Nick Trompert

Nick Trompert is a Sr. Manager. He is responsible for connecting with the best engineering and information technology talent and resources in the world. He is one of the founders of Talent 101 and joined full time after college.