Talent 101 Circuit

Javier – IC Layout Designer

• Principal level RF/Analog/Mixed-Signal IC Layout Designer  with extensive experience in layout floor planning, standard cell planning, hierarchical layout assembly, device matching, place-and-route (P&R) of large digital and analog blocks, shielding and guard ringing, DFM, tape out GDSII format and E-beam mask generation
• Broad and deep knowledge in multiple complex designs for PMIC, analog, digital, mixed-signal, high speed GHz RF, Datapath and standard cells

Wang – Design/Layout Engineer   

• Design/Layout Engineer with over 10 years’ experience dealing with the design/layout of analog and/or mixed signal products
• Design lead of Serial EEPROM (SPI/I2C) products which include analog (voltage/current
  references), and +16V (charge-pumps, regulators, level-shifting) circuit blocks
• Design lead of RTCC products (SPI/I2C) which include analog (voltage/current references), memory (EEPROM, SRAM), and +16V (charge-pumps, regulators, level-shifting) circuit blocks

Jake – PCB Layout Designer   

• Mentor Expedition 
• Mentor Design Capture
• Mentor DX Designer
• Cadence Allegro

Vidal – Layout Engineer  

• Perform chip level physical Analog Custom Layout design using latest Cadence Virtuoso Layout Editor VLE/VXL layout tools and techniques for optimization of speed, power, and area (.35um & .7um technologies).
• Excellent device matching techniques along with debug and verification ability at device, cell, block, and chip levels.

Sophia – Senior Analog RF Layout Design Engineer

• Cadence Virtuoso 6.1.7 Open Access, Cadence GXL/VXL, Cadence Diva, Cadence Dracula

• Cadence Assura for LVS/DRC/Parasitic Extraction

• Cadence VCR, Cadence P-Cell Creation, Cadence Multiple Part Path

• Cadence Shape-Based Router (CSR) Cadence Space-Based Router

Jake – PCB Layout Designer

• Mentor Expedition

• Mentor Design Capture

• Mentor DX Designer

• Cadence Allegro

Bonnie – Layout Design Engineer  

• Layout Design Engineer with extensive experience in all phases of microchip layout design and ability to work independently to meet aggressive deadlines
• Strengths in analog layout, RF design techniques, including shielding, matching, common centroiding cross-coupling, interdigitation etc.
• Effective Executive layouts from floor plan to tape out, enabling design engineers to analyze, simulate, and create design improvements in a synergistic and timely manner.

Maria– Senior Layout Engineer   

• Senior IC Layout Designer/Leader with strong people, team-building, and project management skills
• Lead Layout Designer, for new Rad Hard Microwave 10GHZ designs.
• Utilizing SiGe IBM,HP for RF circuitry (TX, RX) etc

Ahmed – Senior Analog RF Layout Design Engineer 

• Cadence Virtuoso 6.1.7 Open Access, Cadence GXL/VXL, Cadence Diva, Cadence Dracula
• Cadence Assura for LVS/DRC/Parasitic Extraction
• Cadence VCR, Cadence P-Cell Creation, Cadence Multiple Part Path
• Cadence Shape Based Router  (CSR) Cadence  Space Based Router
• Cadence Automatic Router Cadence Wire Assistant

Shima – Senior IC Layout Design Engineer 

• Lead, schedule and plan circuit projects that are both efficient and cost effective within time scheduled
• Supervised and instruct team members through all phases of project
• Created layout that can and will save silicon waste and dollars
• Created the tightest compaction of layout possible
• Performed layout of Analog and Digital circuits in 250nm, 180nm, 130nm, 90nm, 65nm, 45nm, 40nm, 28nm and 10nm/finfet technologies
• Performed layout of RF/Analog circuits