Talent 101 Circuit

Ali – Analog Layout Design Engineer

• 10+ years’ experience
• Experience working on  Optical, Voice and Memory chips
• Experience with both Chip and Block level work
• DAC, Controller, Bi-CMOS, CMOS, LDO, PLL, ADC
• Global Foundries, TSMC, Xfab Processes

Vidal - Layout Engineer

• Perform chip level physical Analog Custom Layout design using latest Cadence Virtuoso Layout Editor VLE/VXL layout tools and techniques for optimization of speed, power, and area (.35um & .7um technologies).
• Excellent device matching techniques along with debug and verification ability at device, cell, block, and chip levels.
• Verify correctness and integrity of layout using expert checking (hierarchical) skills using DIVA and Calibre for DRC/Extraction/LVS/ERC/Antenna Checks.

Adam – Senior Layout Designer

• Experienced in digital layout in areas such as microprocessor, Digital Signal Processor (DSP), System on a Chip (SoC), RAM, EPROM, and fully differential logic
• Experienced in analog layout in areas such as Comparators, Digital to Analog Converters (DAC), Phase Lock Loops (PLL), Bandgaps, and Voltage Regulators

Maria– Senior Layout Engineer  

• Senior IC Layout Designer/Leader with strong people, team-building, and project management skills.
• Lead Layout Designer, for new Rad Hard Microwave 10GHZ designs.
• Utilizing SiGe IBM,HP for RF circuitry (TX, RX), etc.
• Created various IP in 45nm blocks.
• Trained on the new 10nm FinFET process.
• Performed layout on various FinFET Macros.
• Utilizing bicmos 8HP- 90nm, and cms 9flp-130nm for RF Circuitry.
• Currently kicking off new 14nm FinFET IBM projects for various new designs.

Rene – Circuit Design/Layout Engineer

• CMOS Digital 16x16 crossbar switch - Tools: Cadence Virtuoso.
• Designed a digital switch using 16:1 multiplexer and 64-bit shift register on IBM 180 nm CMOS technology.
• Performed DRC, LVS and parasitic extraction along with post-layout simulation for the PCB layout of the circuit.
• Achieved an overall speed of 22.93 GHz for the entire circuit.
• Datapath synchronous controller design - Tools: Altera Quartus II.
• Designed an ASIC using a datapath and controller to perform the Newton-Raphson equation to calculate inverse of a number.
• Modeled the controller using only Verilog and used schematic capture and Verilog for the datapath.
• Worked on block level synthesis, circuit debugging and static timing analysis on the entire design.
• CMOS DC-DC boost converter - Tools: Cadence Virtuoso.
• Designed and simulated a DC-DC converter using boost topology which increases a low input dc voltage to a high dc voltage.
• Utilized the analog design environment on Cadence to run transient and dc simulations on multiple nodes of the circuit.
• Obtained a dc output of 1.5 V for a dc input of 0.8 V using TSMC 130 nm CMOS technology.
• Master of Science in Electrical Engineering.

Jake – PCB Layout Designer

• Mentor Expedition
• Mentor Design Capture
• Mentor DX Designer
• Cadence Allegro
• Cadence HDL
• OrCAD/Cadence Design Entry CIS
• Altium
• Pads
• Seica Viva
• AAS Electronics Engineering Technologies