Talent 101 Circuit

Layout Engineer with Chip-Level Analog Layout Design Experience

Posted on December 13, 2017 by Kent Smith

Vidal - Layout Engineer

  • Perform chip level physical Analog Custom Layout design using latest Cadence Virtuoso Layout Editor VLE/VXL layout tools and techniques for optimization of speed, power, and area (.35um & .7um technologies).
  • Excellent device matching techniques along with debug and verification ability at device, cell, block, and chip levels.
  • Verify correctness and integrity of layout using expert checking (hierarchical) skills using DIVA and Calibre for DRC/Extraction/LVS/ERC/Antenna Checks.

Topics: Layout Designer, Layout Engineer

Kent Smith

Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.

kents@talent-101.com