Talent 101 Circuit

Eva – FPGA/ASIC Design Engineer   

• High speed, high throughput, low latency FPGA design architecture for network devices and high-performance computation systems
• Extensive experience with Xilinx multigigabit transceivers (GTY, GTX, GTH, GTP) in different modes of operation with data rates from 100 Mbit/s up to 25 Gbit/s, experience with top families of Xilinx FPGAs

Auri – Analog IC Design Engineer

• 10+ years of experience in technical leadership and development of innovative analog, mixed-signal, and power management ICs. 
• Design experience in Bipolar, CMOS, BiCMOS, High-Voltage BCD, LDMOS.

Grayson – Physical Design Engineer

• Experienced Physical Design Engineer in high-technology industry with proven expertise worked on numerous ASIC chip designs using various technology processes and challenging designs in advance CMOS technology nodes. 
• Work experience on both SOC and CPU designs.

Rene – Design Engineer

• Design Engineer / Project Manager offering over 10+ years of experience including HVAC design, plant piping systems (cooling and boiler), duct-work systems, and energy management systems.
• Currently using Revit Suite 2016 on Pharmaceuticals projects Mechanical/Electrical.
• Received Citi-Multi Diamond Designer certification for VAR systems 9/21/2010.

Karthik – Design Engineer  

• 1-year experience as Design Trainee intern at VAP Engineering Industries, increased efficiency and profits by 2% by changing products design.
• 1+ year experience in cad designing on Automotive Part Components.
• Simulated CFD problems on Exhaust manifolds and heat exchangers using Ansys (Fluent) workbench.

Guadalupe – Physical Design Engineer 

• Extensive experience in Transistor Level Circuit Design, ASIC Physical Implementation and Custom Layout Design from high performance Microprocessors to low power high speed ASIC and Mix-signal chip integration.
• Successfully taped out multiple microprocessor and SoC, SRAM IP and standard cell libraries into 16 process nodes. In depth Physical Design experience in dual pattern FinFET technologies including Samsung, TSMC and Intel 20nm, 14nm, 16nm, 10nm, 7nm and 5nm FinFET process.

Nihal – Analog Design Engineer 

POWER SUPPLIES:

AJ – Design Verification Engineer 

• Design Verification + Emulation Engineer, with hands-on technical experience in ASIC & FPGA Verification and Emulation. 
• Expert knowledge in advanced design verification using System Verilog & UVM.

Wayne – Hardware (ARM/FPGA) Design/Verification Validation Engineer 

• Testing and collecting of data of semiconducting devices on a multi-test handler 
• Assembling customer samples for use in prototype devices
• Characterizing temperature data during stress testing

Lorenz – Physical Design Engineer  

• Physical Design
• Block level Implementation and physical design of various blocks for 7nm processor. 
• Synthesis, place and route, timing, clock tree synthesis, scan chain.  IR and EM study and fixes. DRC, LVS clean up
• Execution Unit