Experienced Physical Design Engineer in high-technology industry with proven expertise worked on numerous ASIC chip designs using various technology processes and challenging designs in advance CMOS technology nodes.
Extensive experience in Transistor Level Circuit Design, ASIC Physical Implementation and Custom Layout Design from high performance Microprocessors to low power high speed ASIC and Mix-signal chip integration.
Successfully taped out multiple microprocessor and SoC, SRAM IP and standard cell libraries into 16 process nodes. In depth Physical Design experience in dual pattern FinFET technologies including Samsung, TSMC and Intel 20nm, 14nm, 16nm, 10nm, 7nm and 5nm FinFET process.
10+ years of experience in technical leadership and development of innovative analog, mixed-signal, and power management ICs.
Design experience in Bipolar, CMOS, BiCMOS, High-Voltage BCD, LDMOS.
Experience in design of switching regulator systems and a variety of custom analog circuits towards power management products, Programmable Rotary Encoder, and high-speed communications products.
Experience with high performance voltage and current mode switching DC/DC converters and controllers, LDOs, LED drivers, linear voltage regulators, bandgap references including ultra-low power bandgaps, effective bias circuits, protection circuits, A/D-D/A data converters, precision amplifiers and comparators, oscillators, PLLs, VCOs, High Speed Custom Digital circuits and IOs, various sensors, and others.