Talent 101 Circuit

Larry – Analog IC Design Engineer   

• 10+ years of experience in technical leadership and development of innovative analog, mixed-signal, and power management ICs. 
• Design experience in Bipolar, CMOS, BiCMOS, High-Voltage BCD, LDMOS. 
• Experience in design of switching regulator systems and a variety of custom analog circuits towards power management products, Programmable Rotary Encoder, and high-speed communications products.
• Experience with high performance voltage and current mode switching DC/DC converters and controllers, LDOs, LED drivers, linear voltage regulators, bandgap references including ultra-low power bandgaps, effective bias circuits, protection circuits, A/D-D/A data converters, precision amplifiers and comparators, oscillators, PLLs, VCOs, High Speed Custom Digital circuits and IOs, various sensors, and others.

Bob – Analog IC Design Engineer 

• Fin Fet 16nm & 14nm CMOS and SiGe analog designer
• Developed GSM/WCDMA radio chips for Sequoia Communications
• Designed PLL SONET Fiber-optic communication chips for Applied Micro Circuits Corp

Kale – Custom IC Layout Engineer   

• IC physical design engineer with over 10 years of experience which includes full custom analog, digital place and route, and chip-level mixed-signal integration. 
• Comfortable at all levels of hierarchy and leading teams. 
• Experienced in defining, documenting, and training team members in Layout Methodologies for the most current process nodes.

Tang – Analog/Mixed Signal IC Design Engineer 

• Semiconductor advance node processes: BiCMOS, CMOS and FinFET. Create custom design reference database for advanced process nodes: FinFET 14nm, 11nm, 10nm, 8nm, 7nm.
• Experience with op amps, high-speed SerDes designs and adaptation process for serial link.
• Front-to-back experience with transistor level design: Cadence tools (Schematic XL, ADE L/XL, Spectre (RF), Virtuoso Layout XL, PVS DRC / LVS, and QRC extraction).

Wang – Design/Layout Engineer   

• Design/Layout Engineer with over 10 years’ experience dealing with the design/layout of analog and/or mixed signal products
• Design lead of Serial EEPROM (SPI/I2C) products which include analog (voltage/current
  references), and +16V (charge-pumps, regulators, level-shifting) circuit blocks
• Design lead of RTCC products (SPI/I2C) which include analog (voltage/current references), memory (EEPROM, SRAM), and +16V (charge-pumps, regulators, level-shifting) circuit blocks

Akron - Analog IC Design Engineer

• RF/Analog-Mixed Signal IC Design, Layout Design, Verification and Testing
• Experienced in CMOS Circuit Design, ASIC Design and Custom Layout. 
• Experience with industry standard Cadence, Spectre RF, AWR MWO, Eagle CAD PCB design tool

Juan – IC Design Engineer   

• Creative and competent IC design engineer capable of working as an individual contributor or working effectively within a team environment in the technical definition, design and validation of schedule driven mixed signal IP
• Extensive experience in the design, implementation and debug of ESD and latch-up tolerant networks and circuits
• Highly proficient in floor-planning of circuits, ESD/latch-up tolerant layout practices and analog layout techniques

Rick – Design Engineer

• Design Engineer / Project Manager offering over 10+ years of experience including HVAC design, plant piping systems (cooling and boiler), duct-work systems, and energy management systems.
• Currently using Revit Suite 2016 on Pharmaceuticals projects Mechanical/Electrical
• Received Citi-Multi Diamond Designer certification for VAR systems 9/21/2010.

Joe – Analog Design Engineer

• A Digital and Analog Design Engineer with over 10+ years’ experience in hardware and firmware design for control and communications systems.
• Expertise includes:
  • Board-level digital and analog, digital ASIC front end, and FPGA design.
  • Embedded microprocessors and DSP applications, buses and interfaces.

Sophia – Senior Analog RF Layout Design Engineer

• Cadence Virtuoso 6.1.7 Open Access, Cadence GXL/VXL, Cadence Diva, Cadence Dracula

• Cadence Assura for LVS/DRC/Parasitic Extraction

• Cadence VCR, Cadence P-Cell Creation, Cadence Multiple Part Path

• Cadence Shape-Based Router (CSR) Cadence Space-Based Router