Maria– Senior Layout Engineer
- Senior IC Layout Designer/Leader with strong people, team-building, and project management skills.
- Lead Layout Designer, for new Rad Hard Microwave 10GHZ designs.
- Utilizing SiGe IBM,HP for RF circuitry (TX, RX), etc.
- Created various IP in 45nm blocks.
- Trained on the new 10nm FinFET process.
- Performed layout on various FinFET Macros.
- Utilizing bicmos 8HP- 90nm, and cms 9flp-130nm for RF Circuitry.
- Currently kicking off new 14nm FinFET IBM projects for various new designs.