Manuel – Lead Senior System Engineer
- Deep understanding of analog matching requirements, common centroid techniques for minimizing V offsets in matched pairs and other circuits; ensuring high yield processing and circuit performance through the use of identical processing environments/device orientations, dummies, WPE compliant enclosures, etc.; capacitive coupling minimization through the use of spacing and/or co-ax shielding on critical AC signals.
- Full understanding of generation and schematic representation of isolation structures; interdigitation and/or centroiding of matched resistor/capacitor arrays.
- Full understanding of parasitic RC loading on critical signals; antenna effect resolution.
- Extensive experience with clean and effective layout of all common analog sub-blocks up to full chip floor planning.
- Extensive experience with LVS/DRC verification at all levels on most industry standard software.