FPGA/ASIC Design Engineer

Eva – FPGA/ASIC Design Engineer

High speed, high throughput, low latency FPGA design architecture for network devices and high-performance computation systems
Extensive experience with Xilinx multigigabit transceivers (GTY, GTX, GTH, GTP) in different modes of operation with data rates from 100 Mbit/s up to 25 Gbit/s, experience with top families of Xilinx FPGAs
Xilinx Vivado, Xilinx ISE, Modelsim, ISim, ChipScope, Onespin, QuestaSim, Spyglass tools
Algorithm development, improvement and adoption for FPGA
VHDL, System Verilog, design constraining and editing using TCL (Vivado), including non-project mode
Design verification, Formal Verification, simulation, debug
Randomized automatic self-checking testbenches, UVM, formal verification (Onespin)
Low level network protocols
Timing constraints troubleshooting
EMC and signal integrity
Familiar with laboratory test equipment (oscilloscope, spectrum analyzer)
Python to speed up development process
Master of Science in Radio physics & Electronics