Guadalupe – Physical Design Engineer
- Extensive experience in Transistor Level Circuit Design, ASIC Physical Implementation and Custom Layout Design from high performance Microprocessors to low power high speed ASIC and Mix-signal chip integration.
- Successfully taped out multiple microprocessor and SoC, SRAM IP and standard cell libraries into 16 process nodes. In depth Physical Design experience in dual pattern FinFET technologies including Samsung, TSMC and Intel 20nm, 14nm, 16nm, 10nm, 7nm and 5nm FinFET process.
- Proficient with RTL to GDS flows using Synopsys, DC, ICC2, PrimeTime and Cadence Innovus, Tempus, Conformal, Calibre PDV and scripting in Perl and TCL.
- Hands-on expertise in static and dynamic transistor level circuit design, SPICE level simulation and characterization, STA Timing correlation, signal integrity and custom layout.
- Major strengths are in design of high-speed and low power custom macros like Cache, TLB, single and dual port SRAM, ROM, CAM, Register Files, memory compilers development, physical design and verification, Static Timing Analysis, DFT scan and MBIST implementation, clock & power design, and EM/IR analysis.
- Always consistent for delivering on-time by dedication to extremely tight schedules.
- Bachelors, Electrical Engineering Technology.