Bonnie – Layout Design Engineer
- Layout Design Engineer with extensive experience in all phases of microchip layout design and ability to work independently to meet aggressive deadlines
- Strengths in analog layout, RF design techniques, including shielding, matching, common centroiding cross-coupling, interdigitation etc.
- Effective Executive layouts from floor plan to tape out, enabling design engineers to analyze, simulate, and create design improvements in a synergistic and timely manner.
- Software: Candance Opus/Virtuoso/Open Access, GDSII, UNIX Cats, Caliber, Apollo/Avant, Hercules/DRC/LVS Assura, VXL, GXL
- Technologies: CMOS, NMOS, Bipolar, Bicmos, Flash Memory ESDRAM, RF, Analog, Mixed-Signal, TSMCN18 SOI-OA, TSMC, Chartered, IBM CSO17RF, Bicmos8HP, 65nM, 45nM, 40nM, 28nM, 16 finfet, 14nM, 10nM, 5G mMWave, SiGe, 22FDX