Rohan - Digital VLSI Engineer, Mid-level
- Experience in RTL Design (with Verilog HDL and System Verilog) and Logic Synthesis.
- Hands-on experience of Constraint Random based, System Verilog Assertion based, and Coverage driven Functional Verification.
- In-depth knowledge on CMOS Integrated Circuits, Digital Logic Design, ASIC & FPGA Design flow, Static Timing Analysis (STA), Power Analysis & Optimization and DFT (Scan).
- Good understanding of Physical design flow (Floorplanning, Clock Tree Synthesis, Place,and Route) and Physical Verification.
- Good theoretical knowledge on Computer Architecture and organization (Pipelining, Cache Memory, and Tomasulo Algorithm).
- Proficient in Perl scripting using Perl Regular Expressions and Hashes.
- Protocols: UART, I2C, SPI, AMBA – APB, AHB and AXI.
- EDA/ Software Tools: Synopsys VCS, Synopsys DC, Cadence NC Sim, Cadence Virtuoso, Altera Quartus II, ModelSim-Altera, Xilinx ISE, Xilinx Vivado, SPICE, MATLAB.
- Languages: Verilog HDL, System Verilog HDVL, C/ C++ (Object Oriented) Programming, PERL Scripting, UNIX Shell Scripting.
Topics:
Design Engineer,
Digital Designer,
VLSI
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
