Talent 101 Circuit

Senior VLSI Design Engineer Available NOW

Posted on February 05, 2018 by Kent Smith

Ramesh - Senior VLSI Design Engineer

  • Five years of experience as Physical Layer IP Team lead, contributed mainly as Lead Designer.
  • Contributed to multiple activities from Pre-sales to Silicon bring up of PHY IPs.
  • Eleven years of Career in semiconductor field covering Design, Synthesis, STA, FPGA, DFT.
  • Excellent in defining timing constraints including tight Analog to Digital interface signals.
  • Performed STA for 6 Projects.
  • Good combination of strong design skills with in depth timing visualization.
  • Verilog RTL designer with experience in Multi Clock Domain Designs.
  • Expertise in SOC level and IP level DFT Design, Verification and Silicon testing including DC and at speed scan, Memory BIST.
  • Closely works with STA / PnR team to address challenging timing / area closures, ECOs.
  • Performed design evaluation in Xilinx FPGAs.

Topics: Design Engineer, SOC, VLSI

Kent Smith

Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.