Kumar – Senior VLSI Engineer [Available May 1, 2018]
- 7yrs overall industry experience – IP verification (RTL and GLS), FPGA verification and RTL Design.
- Experience in Digital Verification (testbench environment, models, checkers, drivers, functional coverage, assertions and test case development in system Verilog and Verilog languages).
- Experience in using scripting languages like Perl for pre/post-processing of results.
- Experience in Verilog, SV and UVM test bench environments.
- Experience in RTL design.
- Experience in different serial and parallel bus protocols.