Charbel – Physical Design Engineer
- Core experience centered on physical design of large complex CMOS, ASIC, SOC Designs using industry standard tools i.e. Innovus, ICC, talus, and Primetime.
- Responsible for synthesis, formal verification, floor planning (block and top level), power creation and repair, timing driven placement and routing, CTS, timing convergence and analysis, noise convergence and analysis, LVS and DRC.
- Proficient in Cadence's SOC FE, Synopsys' ICC and talus performing synthesis, place and route, timing closure and power analysis.
- Intermediate user of Mentor’s Olympus tool.
- Proficient user of PTSI from Synopsys and Calibre performing LVS/DRC.
- Intermediate skill in TCL Development.
- MS Electrical Engineering
Topics:
Physical Design Engineer
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
