Barbara – Senior ASIC Physical Design Engineer
- 20+ years as a physical designer and 10 tape-outs, from netlist to GDS
- 10+ years of methodology development, understanding and using other company’s methodology
- VLSI design work & custom layout using backend tools from Synopsys(ICC1), Cadence(Innovus)
- Large 28 million gate design, physical partition into three blocks. Intel 10nm process and library and IP
- Create and developed a power estimate to create IR/EM correct power rails using Synopsys tools for TSMC flow
- Extensive use of portable scripting languages for tools flow development
- Versed in Microsoft EXCEL spreadsheet for calculations
- Low power design using the Synopsys UPF methodology and other low power techniques (Vt, MultiVoltage, Power Island)
- Experienced with leading VLSI libraries: INTEL 14/10 nm, TSMC 90/65/20/28HP/14/10, Global Foundries 28HP and UMC 90
- Timing signoff flow using Primetime with AOCV at TSMC 28HP
- Hands-on experience in signal integrity (xtalk/IR), yield improvement (DFM), low power techniques
- Organized and motivated. Able to work in a team environment
- Experienced in methodology or flow development/automation
- Master of Science in Electrical Engineering from NYU-Polytechnic University in Brooklyn, New York
Topics:
Design Engineer,
Physical Design Engineer
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
