Talent 101 Circuit

Design Verification Engineer with Experience in block and SOC  (Available Now)

Posted on April 06, 2018 by Kent Smith

Jeffrey – Design Verification Engineer

  • Extensive experience in the Design Verification in both block and SoC levels 
  • Skilled in directed and constrained-random test benches
  • Proficient in Object-Oriented programming
  • Languages – System Verilog, Verilog, SVA, C, Perl, Shell Scripts, assembly (e200, e500, HC08, HC12)
  • Verification methodologies – UVM, VMM
  • Simulators – VCS, NC Verilog (incisive), Verilog XL
  • Waveform viewers – Debussy, DVE, Signal Scan, Simvision
  • Code coverage tools – HDLscore, Cover Meter
  • Operating systems – UNIX, Linux, AIX, MS Windows
  • Strong verification skills – problem-solving, debugging, verification planning
  • Bachelor of Science in Electrical Engineering

Contact Us About This Candidate

Topics: Design Engineer, SOC, Verification Engineer

Kent Smith

Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.