Pete – Senior Circuit Design Engineer
- Physical Design
- Mixed-Signal Design
- Project Management
- SOC Encounter
- RTL to GDS
- Static Timing Analysis
- Circuit Simulation
- Synthesis
- Spectre/MDL
- EMIR
- Magma
- Virtuoso
- ICC
- HSPICE
- Cadence
- TCL
- Synopsys
- Primetime
- RTL Compiler
- ASIC
- B.S. in Electrical Engineering