Nicholas – Design Verification Engineer
- Extensive experience in the Design Verification at both block and SoC levels.
- Skilled in directed and constrained-random test benches. Proficient in Object-Oriented programming.
- Languages – System Verilog, Verilog, SVA, C, Perl, shell scripts, assembly (e200, e500, HC08, HC12).
- Verification Methodologies – UVM, VMM.
- Simulators – VCS, NC Verilog (Incisive), Verilog XL.
- Waveform Viewers – Debussy, DVE, Signal Scan, SimVision
- Code coverage tools – HDLScore, CoverMeter
- Operating Systems – UNIX, Linux, AIX, MS Windows.
- Strong verification skills – Problem solving, debugging, verification planning.
- Bachelor of Science in Electrical Engineering