At Talent 101, we're constantly working with companies to place quality semiconductor engineers within organizations. Here are just some of the talented individuals we work with that we can place with your company. If you see someone you'd like to have work with you, or know of another talent need, please feel free to contact us.
Digital/Mixed Signal Verification Engineer
Has over 7 years' experience in the semiconductor industry working for companies like Texas Instruments and Intel. Digital design verification, Analog behavioral modeling, Digital design debugging skills, Mixed signal IP verification, Cadence analog and digital Simulation Environments.
Sr. Physical Design Engineer
Has over 15 years of experience in the industry working for companies like Analog Devices and Texas Instruments. Planned and implemented the Timing Closure and Physical Design. Experience working with Block and top level physical design, High speed design closure, STA, Signoff Checks, Design Flow Automation and Multi Voltage and multi power domain designs.
Lead/Sr. Digital Design Engineer
Has over 17 years' experience in the industry working for companies like ON Semiconductor and Alcatel. FPGA-to-ASIC conversions, ASIC-to-ASIC conversions and prime ASIC developments. Responsibilities as technical lead included interfacing with customers, translation of legacy designs into ON technology, RTL code design, synthesis using CAD tools, DFT insertion, functional and test verification, STA, work with physical design engineer for timing closure & signoff, test program development and device specification documentation.
Sr. Design Verification Engineer
Has over 12 years’ experience in the industry working for Renesa’s, Intel, and Texas Instruments. Design Verification specializing in the development and functional and formal verification of Microcontrollers, SoC, and IPs using Verilog, System Verilog, OVM, and assembly language.
PD Architect or ASIC Physical Designer
13+ years’ experience overall industry experience in ASIC Physical design, chip layouts in 28nm, 65nm, 90nm, 0.13um and 0.18um from TSMC/IBM/Global Foundry/Fujitsu and Tower. Flip design, 10 ring, RDL routing bump planning using Rio Magic/Hydra.
Test/Characterization Technician
RF Technician experienced in board level troubleshooting, characterization, soldering and manual testing. Both Wafer and DUT board test and troubleshooting experience. Experience in bench testing tools and LTX ATE equipment. Extensive characterization experience determining and data entry of fail points.
