Test Engineer
Over fifteen years of experience on ATE test development for digital and analog/mixed-signal VLSI production testing in the semiconductor industry. Experienced in IC test methodology development for data converter ADC & DAC, video decoder, audio codec, power management, analog front end (AFE), PLL, digital and mixed-signal products ATE Teradyne A580, Catalyst, Flex, and J750, Eagle ETS364, VLCT, LTX Fusion, loadboard design, schematic capture, PCB layout assisting, test program writing & debugging, and production test release. Design for Test (DFT), ATE test coverage plan, device debug, qualification & characterization, engineering evaluations, statistical analysis & performance, design support, failure analysis, and bench correlation.
Product Test Engineer
Analytical, results-oriented, and bilingual Electrical Engineer with strong communication skills. Team Lead experience and excels in fast-paced environments, with intelligence to rapidly grasp concepts in new technologies, tools, and applications. Fluent in English and Chinese Mandarin, with technical proficiencies in Hardware Design Tools (Mentor Graphics, GerbTool, and Visio), Automated Test Equipments (TI VLCT and HP9495 Testers), Data Analysis Software (DataPower and SpotFire), Production Equipment (Aehr MAX BI systems, Delta and MT handlers, and ThermalStream), and Bench Tools (Oscilloscope, Multimeter, and LabView). Experience with Unix/Linux/Perl/C/Java/PASCAL programming.
Product Engineer
Well versed in New Automotive Products development & RTM release quickly. Quall Testing, FA work, ATE & Bench work. Device setup to Product release, SWRs, Work with various A/Ts, Fabs, Customers. Designed & developed various Probe Cards, Package (Final) Test boards, Handler kits. Developed Digital and Mixed Signal Test programs. Performed Debugging & Characterizations both at Probe & Package (Final Test) level. Experience in various Memory characterizations & debugging: - FLASH, SRAM, DRAM. Worked with pattern conversion tools: ComTest II, Jazz, Autogen, envision Translations. Worked on various ATE Testers: - Teradyne IFLEX, micro FLEX Tester, VLCT Tester, V-Series, LTX Fusion Testers, Teradyne G3, Exposed to Advantest T6575/T6565 system.
RF/Analog/Mixed-Signal IC Design
Experienced in RF/Analog/mixed-signal integrated circuit design. IC design tools and EM simulation software: Cadence IC Spectre RF, Agilent ADS, Hspice, Ansoft HFSS and ASITIC EM field solver. TSMC 0.18μm, 0.35μm and IBM 0.13μm design kits. Custom layout and physical verification using Virtuoso, Diva, Calibre and Assura. PCB design tools and PCB manufacturing/design process. Knowledge of IC design front schematic and back-end layout verification. Matlab, Mathematica, Verilog-A and GPIB commands assisting in circuit design and testing. Experience with test equipment: Characterized ICs using network analyzers, spectrum analyzer, analog signal generator, pulse/pattern generator, digital communication analyzer, noise figure analyzer, component placer and wire bonder.
Physical Design Engineer
Technology experience is a variety and ranges from Synthesis, Physical designs & Electronic Design Automation. Completed work on large processors like Cyrix M2, Mxi, ATI Rage Platform designs, Vitesse Ethernet MAC, ST Microelectronics Telecom ASIC Designs, and Cisco Packet Processors. Many years of experience providing Design Services of various semiconductor customers in North America and EDA pre-sales & technology management roles while working at Cadence. Deep expertise in design environments for Cadence Encounter Digital Implementation platform tools & won various technical benchmarks against the completion. Good Physical Design flow & methodology experience.
Silicon Test Engineers – Available in Bengalore India.
Our team-members have experience in develop Teradyne J750 wafer level and package level test program. Develop probe card and load board design documentation. Collaborate with design and product engineering team to capture test strategy, build test plan. DFT and functional test pattern cyclization, simulation and conversion to industry standard ATE format. Non-volatile memory (NVM) test module development and integration into the master test program. Team up with product engineering team in carrying out Characterization. Data mining using JMP, SEDANA tool. Characterization data correlation with validation team. Develop Qualification program. Test program transfer to production site. Yield analysis and improvement, carry out test time reduction. Spike identification and elimination. Support Gross reproducibility and repeatability (GRR) study. Documentation of lesson learnt, program release note, standard guidelines.
RTL/ASIC Design
Senior Digital Design/Verification Engineer (20 years), who can manage a project and enjoys complex digital chip (ASIC and FPGA) design and verification challenges and EDA tool flow improvements.
Fengchun - Digital Design Engineer
A hardworking and detail-oriented Digital Design Engineer, with a wide range of skills in digital design, verification, debugging, test pattern generation, electronics, components, circuitry, hardware, specification and reliability analysis, interfacing, power, clock, and reset management, and sensor receiving. A communicative and interpersonal team player, with extensive expertise in partnering with multiple levels of an organization to promote synergy and efficiency complete complex projects requiring cross-functional and design for testability. A dynamic and forward-thinking innovator, with a proven ability to exceed goals. VHDL, Verilog and System Verilog, Mentor Graphics, Cadence, Synopsis
Digital Design Engineer
Over 10 years of IC design, development and verification experience. Have complete ASIC design cycle experience from specification, RTL design and verification, synthesis, silicon debug, manufacturing support, and application support to production release on multiple parts. Extensive Lab debug experience. Have experience in FPGA design using Xilinx ISE and Altera's Quartus II foundation. Specialties: Verilog, VHDL, Xilinx ISE, Xilinx Foundation, Altera Quartus II, Chipscope Pro, NCSIM, ModelSim,VCS, Specman, Debussy , Synopsys Design Compiler, Synopsys Primetime, Synopsys Tetramax, Matlab, Simulink, Tcl and C-shell scripting, Spyglass and LEDA, LEC
