Talent 101 Circuit

IC Layout Engineer with 10+ years of experience

Posted on February 06, 2020 by Nick Trompert

Tom– IC Layout Engineer 

  • 10+ years of experience with IC Layout and IC Verification increasing responsibilities in the employment services to the EDA industry. 
  • Mentor Graphics tools: Pyxis, Calibre DRC/LVS, calibredrv, Ample, Design Manager-IC.
  • Tanner tools: L-Edit, Tanner-Calibre integration, Tanner LVS.
  • Cadence tools: Virtuoso, Virtuoso-Calibre integration, Dracula, Assura, SKILL.
  • IC development flow, Schematic/Layout hierarchy, Chip/Block/Cell planning, Verification.
  • CMOS/Bipolar Theories: Logic to schematic convention to layout, Topological layers, Transistor cross-section, Truth table, Fundamental of IC, Full custom layout concepts.
  • Layout techniques: Chip/Block/Cell planning, Power distribution, Busses and Bus routing, Legging Devices, Device Matching, Substrate/Well Taps and Latch up, Guarding, NMOS/PMOS and NPN/PNP Transistors, Capacitors, Resistors, Electrostatic Static Discharge and Diodes, Standard cells, Bond pads, Fuses, Dieseals and Full Chip.
  • Programming languages: Tcl/Tk and Shell scripting.
  • Proficient in Linux, Unix, Windows environments, Microsoft office applications.

Contact Us About This Candidate

Topics: Layout Engineer

Nick Trompert

Nick Trompert is Talent 101’s Marketing Manager. He is responsible for connecting with the best engineering and information technology talent and resources in the world. He is one of the founders of Talent 101 and joined full time after college. He holds a Bachelors Degree in Marketing from Tabor College.

nickt@talent-101.com