Fong – AMS Verification Engineer
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Creating Test Benches in Verilog/SysVerilog
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Verilog A
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Conduct Regression test and compare to spec
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Identify and log bugs
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Work with Design team to resolve issues
Posted on February 13, 2019 by Nick Trompert
Creating Test Benches in Verilog/SysVerilog
Verilog A
Conduct Regression test and compare to spec
Identify and log bugs
Work with Design team to resolve issues
Topics: Verification Engineer
Nick Trompert is a Sr. Manager. He is responsible for connecting with the best engineering and information technology talent and resources in the world. He is one of the founders of Talent 101 and joined full time after college.
nickt@talent-101.com