Sri – Analog and Mixed Signal Circuits and Systems Design Engineer
- Transistor Level Analog Building Blocks
- Modeling and Verification, VerilogA/VerilogAMS, AMS, Cadence
- Layout, VirtuosoXL, ICEDIT and Magic
- System Design, SDM, DC-DC Buck, Boost, Buck-Boost converters
- Process, SMIC 0.13µm, UMC 0.18µm, TSMC 0.35/0.25/0.18/0.13 µm, AMI 0.5 µm, AMS 0.35 µm, Chartered 0.6µm, XFAB 0.35 µm, Allegro’s proprietary 0.5µm. Generic 90nm and 45nm process (Cadence GPDK and other model)
