John - Analog IC Designer
- Designed the following blocks:
- FLL frequency control loop for buck converter
- Rail to Rail PWM comparator
- Band Gap reference
- Compensator
- Reduced current consumption for support blocks (voltage and current reference, etc.) by ~ 50%
- Generated top level layout floorplan
- Optimized Power FET Layout
- Designed 12 bit, inherently monotonic GP DAC with rail to rail output buffer
- Lead designer for PLL
- Designed 50% duty cycle LO dividers capable of dividing by 2, 3, 4, 6, 8, and 12 at input frequencies ranging from 6 to 12 GHz
- Increased 4/5 pre-scalar maximum operating frequency from 8.5 to 11.5 GHz, without increasing the supply voltage
- Performed the characterization on blocks. TRF3765 (wide band PLL) – Lead designer and characterization engineer for RF base station PLL
- TRF3703 (IQ Modulator) ESD test chip. Designed ESD network that properly protected the devices while avoiding the carrier feed-through problem that plagued earlier attempts
- Ph.D. in Electrical Engineering
