Tom – ASIC Design Engineer
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Develop micro-architecture specifications.
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Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.
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Design integration, logic synthesize, and design optimization for timing, area and power.
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Develop front-end methodologies and tool flows.
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Participate in chip bring-up and testing.
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Develop test benches in UVM, System Verilog, Verilog, C, C++ and other languages.
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Write test plans for digital signal processing logic blocks, control logic blocks, general-purpose FMA processor cores and other digital logic devices.
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Write and debug tests for a complex media processor in UVM, System Verilog, Verilog, C, C++, Perl, Python and other languages.
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Develop verification tools.
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Perform coverage analysis using CAD tools.
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Bachelor of Engineering.