Sostenes – FPGA Design Engineer
- 8 Years of strong experience in FPGA/ASIC design and verification flow, Architecture, RTL coding, Functional Verification, Synthesis, Gate level simulations, Static timing analysis (STA), ATPG
- Experience in the design of Xilinx Zynq-7000 Soc, Spartan3E, Lattice LFXP2-40E, and LFXP2-30E & Altera Cyclone III FPGA Boards
- Good Knowledge of ASIC design tools and process flow
- Proficient with C/C++, Verilog HDL, VHDL and System Verilog
- Good knowledge of simulation tools Cadence, Questasim, & Active HDL simulators
- Strong experience in design implementation tools Xilinx Vivado, ISE design flow & Chip Scope Debug Tool
- Developed test environment and set a test plan, Coverage group, Functional coverage
- Verification tests based on constrained random achieve verification metrics
Topics:
Design Engineer,
Verification Engineer
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
