Talent 101 Circuit

ASIC/FPGA Design & Verification Engineer Available

Posted on December 21, 2016 by Kent Smith

Ameen – ASIC/FPGA Design & Verification Engineer

  • Experience in ASIC/FPGA Design and Verification, Computer Architecture, Synthesis, RTL Debug, Python, C.
  • Strong knowledge of creating Test Bench, Static Timing Analysis, ASIC Design flow, CMOS Logic Design.  
  • Understanding of Caches Coherence Protocol (MESI), SoC Integration, Semiconductor Device, and Physics.
  • Knowledge of DFT implementation and Scan insertion, ATPG, Logic BIST.
  • Good team player with excellent communication skills.
  • Languages: Verilog HDL, System Verilog, UVM, C, C++, Java, Data Structures, Perl, Python.
  • EDA Tools: Quartus II, MODELSIM, Synopsys Design Compiler Libero IDE, Oscilloscope, Logic Analyzer, Cadence Virtuoso, Cadence Encounter, NC Verilog, I Verilog, Synopsys VCS (Verilog Compiler Simulator), GTKWave, Synopsys Design Vision, Synplify Pro, UNIX Working Environment.
  • M.S. in Electrical Engineering.

Topics: Design Engineer, Verification Engineer

Kent Smith

Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.

kents@talent-101.com