Jerry – Physical Design Engineer
- Design Tools : Cadence - Virtuoso, Encounter, Assura (DRC, LVS), Spectre, Tempus, Conformal(LEC), Mentor Graphics' Calibre – DRC, LVS, PEX, RVE, Micromagic – SUE (Schematic) & MAX (Layout) Synopsys- Design Vision, Primetime, TetraMAX, ModelSim, Xilinx – ISE
- Programming : Verilog, Perl, C, C++ HSPICE
- Skill Set : RTL Design, RTL Synthesis, netlist to GDSII, Floor Plan, Power Plan, Placement and congestion analysis, CTS, Static Timing analysis(STA), Routing, Physical Verification, SRAM complete design
- Designed low power 8T SRAM of 2Kb memory using IBM 130nm process
- Digital System Design from RTL to GD
- Implementation of 3 stage pipelined Microprocessor on Nexys4 DDR FPGA Board
- Mini Stereo Digital Audio Processor Chip (ASIC) Design
- Library Characterization of standard cells using Silicon Smart
- Master ‘s in Electrical Engineering
