Talent 101 Circuit

Kishan – Design Verification Engineer

• Design Verification (DV) Engineer with 9+ years of experience.
• Strong understanding of ARM CortexM3/A9 based SoC/Sub System verification, Low power simulation, Gate Level Simulation, Coverage closure and Production Pattern Generation.
• Worked on multiple projects in  CortexA9/CortexM3/MIPS based SoC Verification.
• Strong knowledge of Coresight logic used for CortexA9/CortexM3.
• Verification plan development for the given design.
• Gate level simulations ( with and without SDF annotation).
• Low Power Simulations with upf flow.
• Toggle and functional Coverage Closure.
• Good knowledge of ARM AMBA protocols like AHB,AXI,APB,ATB.
• Hands on experience on System Verilog, Verilog, C, ARM assembly and Perl languages.
• Experienced in Functional Pattern Generation and Simulation for SoC (ATE Vectors).
• Bachelor of Technology in Electronics & Communication Engineering.