Talent 101 Circuit

Design Verification Engineer with experience in IC/ASIC design

Posted on April 13, 2018 by Kent Smith

Chang – Design Verification Engineer

  • High-performance IC/ASIC design and verification.  
  • Co-author of two patents.  Strong critical thinking, problem-solving, and planning skills.
  • Expert in UVM, System Verilog, VHDL. 
  • Experienced in developing and deploying new verification methodologies. 
  • Proven track record of developing and delivering high-quality designs on time. 
  • Strong leadership and collaboration skills.
  • Outstanding team player, mentor, and coach.
  • Engineering & Product Management.
  • UVM, Object Oriented Verification
  • Verilog, System Verilog, VHDL, System C
  • RTL Logic Design & Synthesis
  • Cadence, Mentor, and Synopsys Tools
  • C & C++, Object Oriented Design

Contact Us About This Candidate

Topics: Design Engineer, Verification Engineer

Kent Smith

Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.