Samantha – Design Verification Engineer
- Design Verification Engineer with experience in defining testbench architecture, verification planning, and implementation in UVM.
- Knowledge of UVM Environment - Agents (Sequencer, Driver, Monitor), test writing/debug and Coverage.
- Formal Verification, Assertion-based verification.
- Strong knowledge of developing Stimulus, Verification flow, Digital Design, UVM, and OOP.
- Proficient in developing Monitors, Checkers, and Scoreboards in System Verilog.
- Experience on UNIX/LINUX, PERL, Verilog.
- Master of Science in Electrical Engineering
Topics:
Verification Engineer
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
