Sri – Digital Chip Architect
- Strong experience in Architecture/Performance Analysis, Design/ Verification of Digital Design SOCs with focus on processors and memory subsystem.
- Strong experience in Modeling and Debugging complex ASIC systems including multicore processor subsystems.
- Drive solutions from idea to hardware implementation, keeping application requirements/scalability and agility along with Power/Performance/Area trade-offs in mind (using Verilog, System Verilog, VHDL, Shell scripting, Synopsys tools, PERL, SystemC, Microsoft Visual Studio).
- Extensive and progressive cross-functional experience in working with Standards team, Algorithm & Systems team, Application, Benchmarking, Physical Design, and compiler/Software teams with broad knowledge of digital hardware architecture/implementation, providing decisive leadership with analytical rigor identifying improvement areas (Micro-Arch and SOC-Arch) and drive implementation of solutions within PPA budget and schedule.
- Masters in Electrical Engineering.