Manjusha – Digital Design Verification Engineer
- Verification of 2 multi-core (20 processor) complex ASIC SOC designs. Developed Verification plan covering verification strategies - involving module level, inter - module and SOC level functionality tests.
- Performed RTL verification of TI Specific IP’s - PLL controller, Enhanced DMA controller, Interrupt controller, Memory Controllers, VBUS bridges and SCR’s.
- Developed an automated self-checking Random Testbench environment in Specman OVM targeting connectivity faults at various interfaces of a complex SOC.
- Performed Functional coverage for the SOC. Covered all kinds of pattern read/write operations.
- Hands on experience in creating SV UVM Testbench environment.
- MSEE - Circuits & Systems.