Juan - Digital Design and Verification
- Team Leader for multiple IC designs, responsible for guiding projects from feasibility all the way to volume manufacturing.
- Worked on designs ranging from RTL Handoffs (VHDL/Verilog), FPGA to ASIC conversions (Altera/Xilinx) and ASIC to ASIC conversions.
- Designs were packaged in wire bond and flip-chip packaging. Also experienced with die-sales.
- Technology ranged from 500 nm down to 110 nm. Standard-cell and gate-arrays.
- Responsible for IO ring definition and placement. Determined power/gnd pads needed based on SSO calculations.
- Synthesized the design using Design Compiler and RTL Compiler. Used clock-gating cells to minimize power consumption.
- Worked closely with our layout team to close timing. Used Primetime DMSA to make ECOs.
- Experienced in timing constraint development including PLLs, Ring Oscillators, DDR2 and QDR.
- Performed Static Timing Analysis (STA)
- Used Formal Verification tools such as Cadence Encounter Conformal Logic Equivalence Checker (LEC).
- Inserted DFT into the designs via Mentor Graphics Tessent. DFT included scan chains, JTAG boundary scan, Memory BIST and NANDtree.
