Juan - Digital Designer – Front/Back End
- Worked on designs ranging from RTL Handoffs (VHDL/Verilog), FPGA to ASIC conversions (Altera/Xilinx) and ASIC to ASIC conversions.
- Designs were packaged in wire bond, flip-chip packaging, and die-sales.
- Technology ranges from 500 nm down to 110 nm. Standard-cell and gate-arrays.
- Debugging skills with RTL/gate sims and with physical device in-system or in FPGAs.
- Experience with front-end (RTL) and back-end design (Synthesis, DFT, timing constraints).
- Coding experience in Perl, Csh, VHDL, Verilog.
- Experience with NCSim/VerilogXL, Verdi, xperience with TetraMax, Tessent, WinterLogic, LEDA, Synplicity, Design Compiler, RTL Compiler, PrimeTime, LEC.