Talent 101 Circuit

Sydney - Electrical Engineer   

• ASIC design experience in taking designs from the preliminary netlist step through tape out.
• ASIC/FPGA development skills including: logic simulation, formal verification, static timing analysis, floor planning, place and route, timing closure, test vector generation, power analysis, signal integrity checks, LVS/DRC checks, limited logic synthesis and overall EDA methodology/flow compatibility issues.
• Excellent interpersonal skills; quickly establish rapport with people from all management levels and cultural backgrounds, positive, can-do attitude, works well as a member of a team or as a self-directed individual.
• EDA Tools
• Logical Synthesis:  Design Compiler
• HDL simulators/Debugger:  NC Verilog, VCS, Verilog-XL and ModelSim/Verdi
• Static Timing Analysis Tools:  PrimetimeSI/ETS
• Place and Route:  Encounter, IC Compiler, Milkyway data base operations
• Backend Verification:  Calibre
• Formal Verification:  Formality, Conformal
• M.S., Computer Engineering