Ryan – Embedded Hardware Engineer
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10+ years’ experience in ASIC Design
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Analog full chip design, planning, scheduling, and documentation
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Custom design of Analog IP
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Sub-threshold design experience
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Power Management design experience
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Switched capacitor design experience
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Cadence ADEL, ADEXL, AMS, Spectre, UltraSim, Ocean, Hspice, MunEDA, Viewlogic, and Mentor experience
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Experience assisting customers with porting IP from one process to another
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Global Foundries, TSMC, IBM, and JAZZ process experience
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14nm FinFET, 20nm CMOS, 22nm back-gate FDSOI, 28nm CMOS, 40nm CMOS, 130nm FDSOI, 180nm CMOS, 40V BiCMOS, 3u CMOS, 5u CMOS (military)
