Wang – Design/Layout Engineer
- Design/Layout Engineer with over 10 years’ experience dealing with the design/layout of analog and/or mixed signal products
- Design lead of Serial EEPROM (SPI/I2C) products which include analog (voltage/current references), and +16V (charge-pumps, regulators, level-shifting) circuit blocks
- Design lead of RTCC products (SPI/I2C) which include analog (voltage/current references), memory (EEPROM, SRAM), and +16V (charge-pumps, regulators, level-shifting) circuit blocks
- Design/layout lead of 800Mb/s, 1.8V DDR2 Bi-directional I/O pad library using 90nm CMOS process
- Design/layout tools used were Cadence Virtuoso, client’s internal simulation tools
- Design/layout lead of +25V display driver products which included DC/DC converter developed
on 0.35um dual-voltage CMOS process
- Other analog modules included design/layout of voltage/current references, oscillators, Power-On-Reset circuits developed on the same process
- Master of Science in Engineering
Topics:
Design Engineer,
Semiconductor Talent,
Layout Engineer
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
