Kumar – Layout Engineer
- Desigining custom TCell’s for layout using C language in various semiconductor process nodes ranging from 0.18um – 45nm.
- Layout of new memory IP’s in various semiconductor process using L-edit.
- Managing the layouts of existing memory IP’s and performing physical verification using Calibre.
- Design of schematic driven layouts using Tanner EDA.
- Master of Science, Electrical and Computer Engineering
