Gopal – Senior Analog IC Layout Engineer
- Experienced Sr. Analog IC Layout Engineer with 10+ years analog/mixed signal layout and engineering tech experience, working on custom analog/mixed-signal IC layout designs using VirtuosoXL (version IC5.1&6.1), Composer schematics; and Calibre, Assura, Hercules, and Dracula for verification, with Star-RC for parasitic extractions.
- Experienced using Virtuoso Custom Router (VCR), and Astro Digital Place & Route tools.
- Processes used include: TSMC 28nm/40nm, GF 28nm, SMIC 40nm, IBM 0.18um SOI and 0.18um BICMOS, Tower Jazz 0.18um SOI, TSMC 0.6, 0.35 and 0.18um CMOS/BiCMOS.
- A solid background in basic electronics (ASEET) and semiconductor process technologies strengthen my position.
Advanced layout techniques on critical analog blocks were utilized including: use of common-centroid, interdigitation and dummies for optimum matching of differential circuitry, isolation of sensitive devices using guard-rings/substrate rings, extra substrate contacts for 'latch-up' protection, matching and/or minimizing wire lengths and widths for RC control, and other practices for reducing unwanted parasitics.
Topics:
Semiconductor Talent,
Layout Engineer
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
